[PATCH] D153974: [RISCV] Don't include X1 in the X0_PD register pair

[Alex Bradbury via Phabricator via llvm-commits]

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This is perhaps more of a patch for initial discussion and suggestions for alternate approaches rather than ready for full review.

Zdinx on RV32 defines the D instructions as taking even register pairs, and specifies that if using X0 when as a destination then X1 won't be written, and if using X0 as a source then the value is still all 0s (i.e. X1 isn't read). Therefore, it's incorrect to model X0_PD as having X1 as a subregister. This will also be the case for register pairs in Zacas and the P extension (and this patch takes the same approach as D95588 <https://reviews.llvm.org/D95588> does).

This patch introduces a dummy register that is solely used as a subreg alongside X0 in X0_PD. I don't have a test change with this right now, beyond the confusing regalloc change in a seemingly unrelated test.


https://reviews.llvm.org/D153974

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

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