[PATCH] D143759: [AMDGPU] Implement whole wave register spill

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2151
+      if (IsWWMRegSpill) {
+        TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
+                                  RS->isRegUsed(AMDGPU::SCC));
----------------
No need for braces in case of a single instruction.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2159
       MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
+        if (IsWWMRegSpill)
+      TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy());
----------------
Wrong indentation.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2217
+      bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode());
+      if (IsWWMRegSpill) {
+        TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
----------------
Avoid braces.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143759/new/

https://reviews.llvm.org/D143759