[PATCH] D152928: [RFC][DAG] Initially add nodes in the worklist in topological order.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/X86/avx2-shift.ll:416
   ret <16 x i16> %c
 }
 
----------------
Many of the vector regressions are due to X86's combineVectorTruncation fold that is destroying truncate patterns too soon. We should be able to get rid of it with a little more work.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152928/new/

https://reviews.llvm.org/D152928