[llvm] 8de9c1a - [AArch64] Make tests more robust (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-06-28T14:51:55+02:00
New Revision: 8de9c1ab5128568ce72edfa8c951975b83845242

URL: https://github.com/llvm/llvm-project/commit/8de9c1ab5128568ce72edfa8c951975b83845242
DIFF: https://github.com/llvm/llvm-project/commit/8de9c1ab5128568ce72edfa8c951975b83845242.diff

LOG: [AArch64] Make tests more robust (NFC)

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/aarch64-dup-dot-crash.ll
    llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/aarch64-dup-dot-crash.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-dot-crash.ll
index ebd7a8fce9e8a..a4284b9682115 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-dot-crash.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-dot-crash.ll
@@ -5,7 +5,7 @@
 ; generated. Where it tries to generate a ZextOrTrunc node with floating point
 ; type resulting in a crash.
 ; See https://reviews.llvm.org/D128144#4280024 for context
-define void @dot_product(double %a) {
+define double @dot_product(double %a) {
 ; CHECK-LABEL: dot_product:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov d1, #1.00000000
@@ -14,7 +14,9 @@ define void @dot_product(double %a) {
 ; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    fadd d0, d0, d1
 ; CHECK-NEXT:    fsqrt d0, d0
+; CHECK-NEXT:    fmul d2, d0, d1
 ; CHECK-NEXT:    fcmp d0, #0.0
+; CHECK-NEXT:    fcsel d0, d1, d2, gt
 ; CHECK-NEXT:    ret
 entry:
   %fadd = call double @llvm.vector.reduce.fadd.v3f64(double %a, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 0.000000e+00>)
@@ -29,10 +31,10 @@ entry:
 
 bb.1:
   %mul.2 = fmul double %shuffle.1, 0.000000e+00
-  br label %exit
+  ret double %mul.2
 
 exit:
-  ret void
+  ret double 0.0
 }
 
 declare double @llvm.sqrt.f64(double)

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
index 57f7a66cbab69..3ed5db358e091 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
@@ -645,13 +645,15 @@ entry:
 ; CHECK-MACHO: ldp	x20, x19, [sp], #32
 ; CHECK-MACHO: ret
 
+declare void @use(ptr)
 
-define void @realign_conditional(i1 %b) {
+define void @realign_conditional(i1 %b, ptr %p) {
 entry:
   br i1 %b, label %bb0, label %bb1
 
 bb0:
   %MyAlloca = alloca i8, i64 64, align 32
+  store ptr %MyAlloca, ptr %p
   br label %bb1
 
 bb1:
@@ -665,18 +667,20 @@ bb1:
 ; CHECK:  tbz  {{.*}} .[[LABEL:.*]]
 ; Stack is realigned in a non-entry BB.
 ; CHECK:  sub  [[REG:x[01-9]+]], sp, #64
-; CHECK:  and  sp, [[REG]], #0xffffffffffffffe0
+; CHECK:  and  [[REG]], [[REG]], #0xffffffffffffffe0
+; CHECK:  mov  sp, [[REG]]
 ; CHECK:  .[[LABEL]]:
 ; CHECK:  ret
 
 
-define void @realign_conditional2(i1 %b) {
+define void @realign_conditional2(i1 %b, ptr %p) {
 entry:
   %tmp = alloca i8, i32 16
   br i1 %b, label %bb0, label %bb1
 
 bb0:
   %MyAlloca = alloca i8, i64 64, align 32
+  store ptr %MyAlloca, ptr %p
   br label %bb1
 
 bb1:
@@ -691,7 +695,8 @@ bb1:
 ; CHECK:  mov   x19, sp
 ; Stack is realigned in a non-entry BB.
 ; CHECK:  sub  [[REG:x[01-9]+]], sp, #64
-; CHECK:  and  sp, [[REG]], #0xffffffffffffffe0
+; CHECK:  and  [[REG]], [[REG]], #0xffffffffffffffe0
+; CHECK:  mov  sp, [[REG]]
 ; CHECK:  .[[LABEL]]:
 ; CHECK:  ret