[PATCH] D153864: [RISCV] Lower interleave2 intrinsics to vsseg2

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 535302.
luke added a comment.

Address comment and refactor isLegalInterleavedAccessType a bit


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153864/new/

https://reviews.llvm.org/D153864

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

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