[PATCH] D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9378
+      SDValue NewWOp =
+          DAG.getNode(ISD::SHL, DL, MVT::i64, NewOp0, NewOp1, Flags);
       SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
----------------
I’m not sure this is correct. We used ANY_EXTEND for the value to be shifted. That creates a new unknown sign bit. We can no longer be sure that wrap does not occur relative to that unknown sign.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153947/new/

https://reviews.llvm.org/D153947