[llvm] 1876592 - [test] Regenerate some tests
Arthur Eubanks via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 16:54:22 PDT 2023
Author: Arthur Eubanks
Date: 2023-06-27T16:53:50-07:00
New Revision: 1876592ce3e7acfe3a143312815a7ebedcf60b4b
URL: https://github.com/llvm/llvm-project/commit/1876592ce3e7acfe3a143312815a7ebedcf60b4b
DIFF: https://github.com/llvm/llvm-project/commit/1876592ce3e7acfe3a143312815a7ebedcf60b4b.diff
LOG: [test] Regenerate some tests
Added:
Modified:
llvm/test/Transforms/EarlyCSE/fence.ll
llvm/test/Transforms/GVN/fence.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/EarlyCSE/fence.ll b/llvm/test/Transforms/EarlyCSE/fence.ll
index 1dbf666dfa5f0..8ccf73e14e8ff 100644
--- a/llvm/test/Transforms/EarlyCSE/fence.ll
+++ b/llvm/test/Transforms/EarlyCSE/fence.ll
@@ -1,20 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=early-cse -earlycse-debug-hash < %s | FileCheck %s
-; RUN: opt < %s -S -passes='early-cse<memssa>' | FileCheck %s
; NOTE: This file is testing the current implementation. Some of
-; the transforms used as negative tests below would be legal, but
+; the transforms used as negative tests below would be legal, but
; only if reached through a chain of logic which EarlyCSE is incapable
; of performing. To say it
diff erently, this file tests a conservative
; version of the memory model. If we want to extend EarlyCSE to be more
; aggressive in the future, we may need to relax some of the negative tests.
-; We can value forward across the fence since we can (semantically)
+; We can value forward across the fence since we can (semantically)
; reorder the following load before the fence.
define i32 @test(ptr %addr.i) {
-; CHECK-LABEL: @test
-; CHECK: store
-; CHECK: fence
-; CHECK-NOT: load
-; CHECK: ret
+; CHECK-LABEL: define i32 @test
+; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence release
+; CHECK-NEXT: ret i32 5
+;
store i32 5, ptr %addr.i, align 4
fence release
%a = load i32, ptr %addr.i, align 4
@@ -23,11 +24,12 @@ define i32 @test(ptr %addr.i) {
; Same as above
define i32 @test2(ptr noalias %addr.i, ptr noalias %otheraddr) {
-; CHECK-LABEL: @test2
-; CHECK: load
-; CHECK: fence
-; CHECK-NOT: load
-; CHECK: ret
+; CHECK-LABEL: define i32 @test2
+; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {
+; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence release
+; CHECK-NEXT: ret i32 [[A]]
+;
%a = load i32, ptr %addr.i, align 4
fence release
%a2 = load i32, ptr %addr.i, align 4
@@ -37,18 +39,20 @@ define i32 @test2(ptr noalias %addr.i, ptr noalias %otheraddr) {
; We can not value forward across an acquire barrier since we might
; be syncronizing with another thread storing to the same variable
-; followed by a release fence. If this thread observed the release
+; followed by a release fence. If this thread observed the release
; had happened, we must present a consistent view of memory at the
; fence. Note that it would be legal to reorder '%a' after the fence
; and then remove '%a2'. The current implementation doesn't know how
; to do this, but if it learned, this test will need revised.
define i32 @test3(ptr noalias %addr.i, ptr noalias %otheraddr) {
-; CHECK-LABEL: @test3
-; CHECK: load
-; CHECK: fence
-; CHECK: load
-; CHECK: sub
-; CHECK: ret
+; CHECK-LABEL: define i32 @test3
+; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {
+; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[A2:%.*]] = load i32, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[A2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
%a = load i32, ptr %addr.i, align 4
fence acquire
%a2 = load i32, ptr %addr.i, align 4
@@ -56,16 +60,18 @@ define i32 @test3(ptr noalias %addr.i, ptr noalias %otheraddr) {
ret i32 %res
}
-; We can not dead store eliminate accross the fence. We could in
+; We can not dead store eliminate accross the fence. We could in
; principal reorder the second store above the fence and then DSE either
; store, but this is beyond the simple last-store DSE which EarlyCSE
; implements.
define void @test4(ptr %addr.i) {
-; CHECK-LABEL: @test4
-; CHECK: store
-; CHECK: fence
-; CHECK: store
-; CHECK: ret
+; CHECK-LABEL: define void @test4
+; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence release
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: ret void
+;
store i32 5, ptr %addr.i, align 4
fence release
store i32 5, ptr %addr.i, align 4
@@ -75,11 +81,13 @@ define void @test4(ptr %addr.i) {
; We *could* DSE across this fence, but don't. No other thread can
; observe the order of the acquire fence and the store.
define void @test5(ptr %addr.i) {
-; CHECK-LABEL: @test5
-; CHECK: store
-; CHECK: fence
-; CHECK: store
-; CHECK: ret
+; CHECK-LABEL: define void @test5
+; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: ret void
+;
store i32 5, ptr %addr.i, align 4
fence acquire
store i32 5, ptr %addr.i, align 4
diff --git a/llvm/test/Transforms/GVN/fence.ll b/llvm/test/Transforms/GVN/fence.ll
index ef26dde4520a3..f2b1538843681 100644
--- a/llvm/test/Transforms/GVN/fence.ll
+++ b/llvm/test/Transforms/GVN/fence.ll
@@ -1,14 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=gvn < %s | FileCheck %s
@a = external constant i32
; We can value forward across the fence since we can (semantically)
; reorder the following load before the fence.
define i32 @test(ptr %addr.i) {
-; CHECK-LABEL: @test
-; CHECK: store
-; CHECK: fence
-; CHECK-NOT: load
-; CHECK: ret
+; CHECK-LABEL: define i32 @test
+; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
+; CHECK-NEXT: store i32 5, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence release
+; CHECK-NEXT: ret i32 5
+;
store i32 5, ptr %addr.i, align 4
fence release
%a = load i32, ptr %addr.i, align 4
@@ -17,10 +19,11 @@ define i32 @test(ptr %addr.i) {
; Same as above
define i32 @test2(ptr %addr.i) {
-; CHECK-LABEL: @test2
-; CHECK-NEXT: fence
-; CHECK-NOT: load
-; CHECK: ret
+; CHECK-LABEL: define i32 @test2
+; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
+; CHECK-NEXT: fence release
+; CHECK-NEXT: ret i32 0
+;
%a = load i32, ptr %addr.i, align 4
fence release
%a2 = load i32, ptr %addr.i, align 4
@@ -35,11 +38,15 @@ define i32 @test2(ptr %addr.i) {
; property. We expect to eventually see the value of store by
; another thread when spinning on that location.
define i32 @test3(ptr noalias %addr.i, ptr noalias %otheraddr) {
-; CHECK-LABEL: @test3
-; CHECK: load
-; CHECK: fence
-; CHECK: load
-; CHECK: ret i32 %res
+; CHECK-LABEL: define i32 @test3
+; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[A2:%.*]] = load i32, ptr [[ADDR_I]], align 4
+; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[A2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
; the following code is intented to model the unrolling of
; two iterations in a spin loop of the form:
; do { fence acquire: tmp = *%addr.i; ) while (!tmp);
@@ -57,12 +64,13 @@ define i32 @test3(ptr noalias %addr.i, ptr noalias %otheraddr) {
; across both the fences, because the load is from
; a constant memory location.
define i32 @test4(ptr %addr) {
-; CHECK-LABEL: @test4
-; CHECK-NOT: load
-; CHECK: fence release
-; CHECK: store
-; CHECK: fence seq_cst
-; CHECK: ret i32 0
+; CHECK-LABEL: define i32 @test4
+; CHECK-SAME: (ptr [[ADDR:%.*]]) {
+; CHECK-NEXT: fence release
+; CHECK-NEXT: store i32 42, ptr [[ADDR]], align 8
+; CHECK-NEXT: fence seq_cst
+; CHECK-NEXT: ret i32 0
+;
%var = load i32, ptr @a
fence release
store i32 42, ptr %addr, align 8
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