[llvm] 49428ba - [RISCV] Fix a typo in a comment
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 13:08:20 PDT 2023
Author: Philip Reames
Date: 2023-06-27T13:08:11-07:00
New Revision: 49428bad5852551d7b4fb70a70939572a79da730
URL: https://github.com/llvm/llvm-project/commit/49428bad5852551d7b4fb70a70939572a79da730
DIFF: https://github.com/llvm/llvm-project/commit/49428bad5852551d7b4fb70a70939572a79da730.diff
LOG: [RISCV] Fix a typo in a comment
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 960e6cbae3003..bebafb74fa947 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3423,7 +3423,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
}
// Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to
-// (MMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
+// (VMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) {
#define CASE_VMERGE_TO_VMV(lmul) \
case RISCV::PseudoVMERGE_VVM_##lmul##_TU: \
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