[llvm] d983e83 - [RISCV] Simplify pseudo classes used by v(f)merge [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 27 13:02:08 PDT 2023
Author: Philip Reames
Date: 2023-06-27T13:01:58-07:00
New Revision: d983e833dcbbad11501203c884959cca6562fd25
URL: https://github.com/llvm/llvm-project/commit/d983e833dcbbad11501203c884959cca6562fd25
DIFF: https://github.com/llvm/llvm-project/commit/d983e833dcbbad11501203c884959cca6562fd25.diff
LOG: [RISCV] Simplify pseudo classes used by v(f)merge [nfc]
This is mostly hand inlining multiclass definitions, and simplifying for the fact that non-default template values were never actually used.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index e5fdd7752efd2..5a213082e9e0c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2254,13 +2254,10 @@ multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
m.vrclass, m.vrclass, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
- string Constraint = ""> {
- def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" :
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, m.vrclass, m, CarryIn, Constraint>;
+multiclass VPseudoTiedBinaryV_VM<LMULInfo m> {
+ def "_VVM" # "_" # m.MX # "_TU" :
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, m.vrclass, m, 1, "">;
}
multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
@@ -2272,13 +2269,10 @@ multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
m.vrclass, GPR, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
- string Constraint = ""> {
- def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, GPR, m, CarryIn, Constraint>;
+multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {
+ def "_VXM" # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, GPR, m, 1, "">;
}
multiclass VPseudoVMRG_FM {
@@ -2311,13 +2305,10 @@ multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
m.vrclass, simm5, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
- string Constraint = ""> {
- def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, simm5, m, CarryIn, Constraint>;
+multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
+ def "_VIM" # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, simm5, m, 1, "">;
}
multiclass VPseudoUnaryVMV_V_X_I {
@@ -3014,19 +3005,25 @@ multiclass VPseudoVMRG_VM_XM_IM {
defvar ReadVIMergeV_MX = !cast<SchedRead>("ReadVIMergeV_" # mx);
defvar ReadVIMergeX_MX = !cast<SchedRead>("ReadVIMergeX_" # mx);
- defm "" : VPseudoBinaryV_VM<m>,
- Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM<m>,
- Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_IM<m>,
- Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
+ def "_VVM" # "_" # m.MX :
+ VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, m.vrclass, m, 1, "">;
+ def "_VXM" # "_" # m.MX :
+ VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, GPR, m, 1, "">;
+ def "_VIM" # "_" # m.MX :
+ VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, simm5, m, 1, "">;
// Tied versions to allow codegen control over the tail elements
- defm "" : VPseudoTiedBinaryV_VM<m>,
- Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_XM<m>,
- Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_IM<m>,
- Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
+ def "_VVM" # "_" # m.MX # "_TU" :
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, m.vrclass, m, 1, "">;
+ def "_VXM" # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, GPR, m, 1, "">;
+ def "_VIM" # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
+ m.vrclass, simm5, m, 1, "">;
}
}
@@ -5059,37 +5056,32 @@ multiclass VPatBinaryV_IM<string intrinsic, string instruction,
vti.RegClass, simm5>;
}
-multiclass VPatBinaryV_VM_TAIL<string intrinsic, string instruction,
- bit CarryOut = 0,
- list<VTypeInfo> vtilist = AllIntegerVectors> {
- foreach vti = vtilist in
+multiclass VPatBinaryV_VM_TAIL<string intrinsic, string instruction> {
+ foreach vti = AllIntegerVectors in
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VVM",
- !if(CarryOut, vti.Mask, vti.Vector),
+ vti.Vector,
vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>;
}
-multiclass VPatBinaryV_XM_TAIL<string intrinsic, string instruction,
- bit CarryOut = 0,
- list<VTypeInfo> vtilist = AllIntegerVectors> {
- foreach vti = vtilist in
+multiclass VPatBinaryV_XM_TAIL<string intrinsic, string instruction> {
+ foreach vti = AllIntegerVectors in
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction,
"V"#vti.ScalarSuffix#"M",
- !if(CarryOut, vti.Mask, vti.Vector),
+ vti.Vector,
vti.Vector, vti.Scalar, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.ScalarRegClass>;
}
-multiclass VPatBinaryV_IM_TAIL<string intrinsic, string instruction,
- bit CarryOut = 0> {
+multiclass VPatBinaryV_IM_TAIL<string intrinsic, string instruction> {
foreach vti = AllIntegerVectors in
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VIM",
- !if(CarryOut, vti.Mask, vti.Vector),
+ vti.Vector,
vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul,
vti.RegClass, vti.RegClass, simm5>;
@@ -6736,12 +6728,26 @@ defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;
// We can use vmerge.vvm to support vector-vector vfmerge.
// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses
// int_riscv_vmerge. Support both for compatibility.
-defm : VPatBinaryV_VM_TAIL<"int_riscv_vmerge", "PseudoVMERGE",
- /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
-defm : VPatBinaryV_VM_TAIL<"int_riscv_vfmerge", "PseudoVMERGE",
- /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
-defm : VPatBinaryV_XM_TAIL<"int_riscv_vfmerge", "PseudoVFMERGE",
- /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
+foreach vti = AllFloatVectors in {
+ let Predicates = GetVTypePredicates<vti>.Predicates in {
+ defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM",
+ vti.Vector,
+ vti.Vector, vti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.RegClass,
+ vti.RegClass, vti.RegClass>;
+ defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVMERGE", "VVM",
+ vti.Vector,
+ vti.Vector, vti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.RegClass,
+ vti.RegClass, vti.RegClass>;
+ defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE",
+ "V"#vti.ScalarSuffix#"M",
+ vti.Vector,
+ vti.Vector, vti.Scalar, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.RegClass,
+ vti.RegClass, vti.ScalarRegClass>;
+ }
+}
foreach fvti = AllFloatVectors in {
defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
More information about the llvm-commits
mailing list