[PATCH] D153863: [RISCV] Add tests for stores of vector.interleave2

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll:26
+; CHECK-NEXT:    ret
+     %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
+     store <32 x i1> %res, ptr %p
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IR is typically indented 2 spaces I think.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll:62
+define void @vector_interleave_store_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b, ptr %p) {
+     %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+     store <4 x i64> %res, ptr %p
----------------
Missing CHECK lines


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll:150
+define void @vector_interleave_store_v4f64_v2f64(<2 x double> %a, <2 x double> %b, ptr %p) {
+     %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
+     store <4 x double> %res, ptr %p
----------------
Missing CHECK lines


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153863/new/

https://reviews.llvm.org/D153863