[llvm] 03db28e - [ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d

[Ties Stuij via llvm-commits]

Author: Ties Stuij
Date: 2023-06-27T14:58:22+01:00
New Revision: 03db28edbb71ea62be133d478c872c5d825b7389

URL: https://github.com/llvm/llvm-project/commit/03db28edbb71ea62be133d478c872c5d825b7389
DIFF: https://github.com/llvm/llvm-project/commit/03db28edbb71ea62be133d478c872c5d825b7389.diff

LOG: [ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d

The CPSR registers ops of the instructions constructed in ExpandTMOV32BitImm
were marked as kill, instead of define. Best to use the pre-existing
t1CondCodeOp fn to construct CPSRs.

Reviewed By: simonwallis2

Differential Revision: https://reviews.llvm.org/D153763

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/test/CodeGen/ARM/execute-only.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 0c5f9ac095d0c..bf75e2279b7a1 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -984,18 +984,18 @@ void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
 
   Upper8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill);
+          .add(t1CondCodeOp(true));
 
   LSL_U8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg)
           .addImm(8)
           .add(predOps(ARMCC::AL))
           .setMIFlags(MIFlags);
 
   Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
@@ -1003,7 +1003,7 @@ void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
 
   Lower8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg);
 
   MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
@@ -1011,7 +1011,7 @@ void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
 
   Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   Upper8_15.setMIFlags(MIFlags);

diff  --git a/llvm/test/CodeGen/ARM/execute-only.ll b/llvm/test/CodeGen/ARM/execute-only.ll
index 561053e777690..1123efbc11a75 100644
--- a/llvm/test/CodeGen/ARM/execute-only.ll
+++ b/llvm/test/CodeGen/ARM/execute-only.ll
@@ -1,5 +1,3 @@
-; UNSUPPORTED: expensive_checks
-
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s