[PATCH] D153864: [RISCV] Lower interleave2 intrinsics to vsseg2

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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This patch teaches the RISCV TargetLowering class to lower interleave
intrinsics to vsseg2, so it can lower interleaved stores for scalable vectors.
Previously, we could only lower stores of interleaves for fixed length vectors
with vector shuffles.

This uses the lowerInterleaveIntrinsic interface for the interleaved 
access pass that was added in D146218 <https://reviews.llvm.org/D146218>, and subsumes the DAG combine 
approach taken in D144175 <https://reviews.llvm.org/D144175>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153864

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

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