[PATCH] D153499: [RISCV] Add support for custom CSRs for Sifive S76.
garvit gupta via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 26 22:09:26 PDT 2023
garvitgupta08 updated this revision to Diff 534840.
garvitgupta08 marked an inline comment as not done.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153499/new/
https://reviews.llvm.org/D153499
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/xsfcie-invalid.s
llvm/test/MC/RISCV/xsfcie-valid.s
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D153499.534840.patch
Type: text/x-patch
Size: 11461 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230627/7bc101b6/attachment.bin>
More information about the llvm-commits
mailing list