[llvm] 17aa37d - [SelectionDAG] Add memory size for CSEMap ID calculation

[Craig Topper via llvm-commits]

Author: Alex MacLean
Date: 2023-06-26T16:12:48-07:00
New Revision: 17aa37dd30ca2d0b85a151c0c8102946a2cdee4b

URL: https://github.com/llvm/llvm-project/commit/17aa37dd30ca2d0b85a151c0c8102946a2cdee4b
DIFF: https://github.com/llvm/llvm-project/commit/17aa37dd30ca2d0b85a151c0c8102946a2cdee4b.diff

LOG: [SelectionDAG] Add memory size for CSEMap ID calculation

In NVPTX `ReplaceVectorLoad()`, i1 and i8 types are promoted to i16,
followed by a truncate operation. Thus, v2i8 (or v2i1) and v2i16 will
have the same VTList, which causes a collision in CSEMap.

To differentiate the original VTList, let's add the size in generating
an ID. Otherwise the compiler crashes in refineAlignment:
`MMO->getSize() == getSize() && "Size mismatch!"`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153712

Added: 
    llvm/test/CodeGen/NVPTX/dag-cse.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2e14b698224c0..a9f8037c9c49a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -927,6 +927,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
     ID.AddInteger(MN->getRawSubclassData());
     ID.AddInteger(MN->getPointerInfo().getAddrSpace());
     ID.AddInteger(MN->getMemOperand()->getFlags());
+    ID.AddInteger(MN->getMemoryVT().getRawBits());
   }
 }
 
@@ -8066,6 +8067,7 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
         Opcode, dl.getIROrder(), VTList, MemVT, MMO));
     ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
     ID.AddInteger(MMO->getFlags());
+    ID.AddInteger(MemVT.getRawBits());
     void *IP = nullptr;
     if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
       cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);

diff  --git a/llvm/test/CodeGen/NVPTX/dag-cse.ll b/llvm/test/CodeGen/NVPTX/dag-cse.ll
new file mode 100644
index 0000000000000..0b21cdebd87cd
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/dag-cse.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=nvptx64 | FileCheck %s
+
+%st = type { i8, i8, i16 }
+
+ at a = internal addrspace(1) global %st zeroinitializer, align 8
+ at b = internal addrspace(1) global i32 0, align 8
+ at c = internal addrspace(1) global i32 0, align 8
+
+; Verify that loads with 
diff erent memory types are not subject to CSE
+; once they are promoted to the same type.
+;
+; CHECK: ld.global.v2.u8  {%[[B1:rs[0-9]+]], %[[B2:rs[0-9]+]]}, [a];
+; CHECK: st.global.v2.u8  [b], {%[[B1]], %[[B2]]};
+;
+; CHECK: ld.global.v2.u16 {%[[C1:rs[0-9]+]], %[[C2:rs[0-9]+]]}, [a];
+; CHECK: st.global.v2.u16 [c], {%[[C1]], %[[C2]]};
+
+define void @test1() #0 {
+  %1 = load <2 x i8>, ptr addrspace(1) @a, align 8
+  store <2 x i8> %1, ptr addrspace(1) @b, align 8
+  %2 = load <2 x i16>, ptr addrspace(1) @a, align 8
+  store <2 x i16> %2, ptr addrspace(1) @c, align 8
+  ret void
+}