[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105
+            .addImm(FRMImm);
+        MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
+                                                /*IsImp*/ true));
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We still need to add the RISCV::FRM operand for FRMImm == 7. But we should probably do it in `RISCVTargetLowering::AdjustInstrPostInstrSelection`


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Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:226
+  // to the correct CSR.
+  bit IsRVVFixedPoint = 0;
+  let TSFlags{20} =  IsRVVFixedPoint;
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Something like UsesVXRM is probably better? As we established before, not everything the vector spec calls fixed point uses VXRM. Or make HasRoundOp a 2-bit field that encodings what type of rounding mode?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152996/new/

https://reviews.llvm.org/D152996