[PATCH] D153155: [RISCV] Remove legacy TA/TU pseudo distinction for VID

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 26 12:56:57 PDT 2023


reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:540
 
-class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true, bit IsTernary = false> {
+// Describes the relation of a masked pseudu to the unmasked variants.
+// (HasTU = true, IsCombined = false)
----------------
craig.topper wrote:
> pseudu -> pseudo
I really don't seem to be able to spell in this changeset...


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4565
+                            vti.RegClass:$merge, GPR:$vl, vti.Log2SEW,
+                            TAIL_UNDISTURBED_MASK_UNDISTURBED)>;
       def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
----------------
craig.topper wrote:
> Didn't we just add a `TU_MU` defvar? I thought we were moving to shorter name.
We did.  I'd just written this code in a different order than I'd posted patches and forgot to update.  


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll:12
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr = COPY $v8
-  ; CHECK-NEXT:   %2:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[COPY1]], [[COPY]], 2, 6 /* e64 */, implicit $frm
-  ; CHECK-NEXT:   $v8 = COPY %2
+  ; CHECK-NEXT:   [[PseudoVFADD_VV_M1_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[COPY1]], [[COPY]], 2, 6 /* e64 */, implicit $frm
+  ; CHECK-NEXT:   $v8 = COPY [[PseudoVFADD_VV_M1_]]
----------------
craig.topper wrote:
> Is this change related?
Nope, spurious regen change.  Separate and landed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153155/new/

https://reviews.llvm.org/D153155



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