[llvm] c32c0e1 - [RISCV] Add i32 as a legal type for GPR register class.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-26T12:14:34-07:00
New Revision: c32c0e14d6944d6a0e36191d7b5bf6943f96092e

URL: https://github.com/llvm/llvm-project/commit/c32c0e14d6944d6a0e36191d7b5bf6943f96092e
DIFF: https://github.com/llvm/llvm-project/commit/c32c0e14d6944d6a0e36191d7b5bf6943f96092e.diff

LOG: [RISCV] Add i32 as a legal type for GPR register class.

I'm investigating if it is feasible to have i32 as a legal type for RV64.
The first thing we need to do is make i32 a valid type for the GPR
register class.

We already added f32/f64 as valid types which required adding explicit
types to tablegen patterns. Adding additional types to GPR is free now.

Reviewed By: sunshaoce

Differential Revision: https://reviews.llvm.org/D151177

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 3d006cefe8bb2..b86fbcce9f5ac 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -124,7 +124,7 @@ def XLenRI : RegInfoByHwMode<
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
-def GPR : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPR : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
@@ -135,15 +135,15 @@ def GPR : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
   let RegInfos = XLenRI;
 }
 
-def GPRX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add X0)> {
+def GPRX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add X0)> {
   let RegInfos = XLenRI;
 }
 
-def GPRNoX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, X0)> {
+def GPRNoX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (sub GPR, X0)> {
   let RegInfos = XLenRI;
 }
 
-def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, X0, X2)> {
+def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (sub GPR, X0, X2)> {
   let RegInfos = XLenRI;
 }
 
@@ -151,11 +151,12 @@ def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, X0, X2)>
 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
 // X3, and X4 as it reduces the number of register classes that get synthesized
 // by tablegen.
-def GPRJALR : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, (sequence "X%u", 0, 5))> {
+def GPRJALR : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32,
+                            (sub GPR, (sequence "X%u", 0, 5))> {
   let RegInfos = XLenRI;
 }
 
-def GPRC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPRC : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 10, 15),
     (sequence "X%u", 8, 9)
   )> {
@@ -166,7 +167,7 @@ def GPRC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
 // restored to the saved value before the tail call, which would clobber a call
 // address. We shouldn't use x5 since that is a hint for to pop the return
 // address stack on some microarchitectures.
-def GPRTC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPRTC : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 6, 7),
     (sequence "X%u", 10, 17),
     (sequence "X%u", 28, 31)
@@ -174,12 +175,12 @@ def GPRTC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
   let RegInfos = XLenRI;
 }
 
-def SP : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add X2)> {
+def SP : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add X2)> {
   let RegInfos = XLenRI;
 }
 
 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
-def SR07 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def SR07 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 23)
   )> {