[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4c37d30e22ae: [RISCV] Add support for custom instructions for Sifive S76. (authored by garvitgupta08, committed by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

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