[PATCH] D153793: [RISCV] Fix encoding for Zcb instruction c.sh.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Bit 6 should be 0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153793

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
  llvm/test/MC/RISCV/rv32zcb-valid.s


Index: llvm/test/MC/RISCV/rv32zcb-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32zcb-valid.s
+++ llvm/test/MC/RISCV/rv32zcb-valid.s
@@ -67,7 +67,7 @@
 c.sb a5, 2(a4)
 
 # CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
-# CHECK-ASM: encoding: [0x7c,0x8f]
+# CHECK-ASM: encoding: [0x3c,0x8f]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
 c.sh a5, 2(a4)
 
@@ -116,7 +116,7 @@
 sb a5, 2(a4)
 
 # CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
-# CHECK-ASM: encoding: [0x7c,0x8f]
+# CHECK-ASM: encoding: [0x3c,0x8f]
 sh a5, 2(a4)
 
 # CHECK-ASM-AND-OBJ: c.lbu s0, 0(s1)
@@ -136,5 +136,5 @@
 c.sb s0, (s1)
 
 # CHECK-ASM-AND-OBJ: c.sh s0, 0(s1)
-# CHECK-ASM: encoding: [0xc0,0x8c]
+# CHECK-ASM: encoding: [0x80,0x8c]
 c.sh s0, (s1)
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -174,7 +174,7 @@
 
 def C_SB : CStoreB_rri<0b100010, "c.sb">,
            Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
-def C_SH : CStoreH_rri<0b100011, 0b1, "c.sh">,
+def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
            Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
 }
 


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