[llvm] fe0750b - SeparateConstOffsetFromGEP: Reorder run lines

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2023-06-26T13:58:06-04:00
New Revision: fe0750b97943070c4dc652afa3628aee0b0d0ebb

URL: https://github.com/llvm/llvm-project/commit/fe0750b97943070c4dc652afa3628aee0b0d0ebb
DIFF: https://github.com/llvm/llvm-project/commit/fe0750b97943070c4dc652afa3628aee0b0d0ebb.diff

LOG: SeparateConstOffsetFromGEP: Reorder run lines

Testing codegen in test/Transforms is questionable to begin with, but
it's more reasonable to see failures on the IR half before ISA checks.

Added: 
    

Modified: 
    llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
index 84fc8da006994..5652b6657b536 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_20 \
-; RUN:     | FileCheck %s --check-prefix=PTX
 ; RUN: opt < %s -mtriple=nvptx64-nvidia-cuda -S -passes=separate-const-offset-from-gep,gvn \
 ; RUN:       -reassociate-geps-verify-no-dead-code \
 ; RUN:     | FileCheck %s --check-prefix=IR
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_20 \
+; RUN:     | FileCheck %s --check-prefix=PTX
 
 ; Verifies the SeparateConstOffsetFromGEP pass.
 ; The following code computes