[PATCH] D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[Konstantina Mitropoulou via Phabricator via llvm-commits]

kmitropoulou added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6049
+    // Check if the two compare instructions have a common operand.
+    return LHS0 == RHS0 || LHS1 == RHS1;
+  };
----------------
kmitropoulou wrote:
> kmitropoulou wrote:
> > craig.topper wrote:
> > > What is LHS0 == RHS1 or LHS1 == RHS0 and CCL is the opposite of condition CCR?
> > Let's take the following test case from zbb-cmp-combine.ll:
> > define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
> > ; CHECK-LABEL: no_same_ops:
> > ; CHECK:       # %bb.0:
> > ; CHECK-NEXT:    sltu a1, a0, a1
> > ; CHECK-NEXT:    sltu a0, a2, a0
> > ; CHECK-NEXT:    or a0, a1, a0
> > ; CHECK-NEXT:    ret
> >   %l0 = icmp ult i64 %c, %a
> >   %l1 = icmp ugt i64 %c, %b
> >   %res = or i1 %l0, %l1
> >   ret i1 %res
> > 
> > Here, the predicate of the second compare instruction(ugt) is replaced with ult and the operands are swapped and we have
> > 
> > icmp ult i64 %c, %a
> > icmp ult i64 %b, %c
> > 
> > If we apply the proposed optimization, then we will have correctness issues.
> > 
> I am sorry I misunderstood it earlier. I will add this case.
>> What is LHS0 == RHS1 or LHS1 == RHS0 and CCL is the opposite of condition CCR?

I added this case.




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  https://reviews.llvm.org/D153502/new/

https://reviews.llvm.org/D153502