[PATCH] D153743: [RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node

[Yunze Zhu(Thead) via Phabricator via llvm-commits]

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There is issue: https://github.com/llvm/llvm-project/issues/63515
This issue is because when expanding SPLAT_VECTOR_SPLIT_I64_VL node, only memoperand is used to create dependency. However in ScheduleDAGNodes, dependency is checked with chain only, and breaks order of store/load instructions. 
I think in llvm.bitreverse.nxv2i64 intrinsic  SPLAT_VECTOR_SPLIT_I64_VL nodes are parallel processed, so no chain should be add to these nodes.
Using temporary in expanding SPLAT_VECTOR_SPLIT_I64_VL node can keep vlse instruction get correct value no matter order of store instructions is changed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153743

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll

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