[PATCH] D153490: [RISCV] Properly handle partial writes in isConvertibleToVMV_V_V.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 25 23:09:11 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb105b3266fa0: [RISCV] Properly handle partial writes in isConvertibleToVMV_V_V. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153490/new/
https://reviews.llvm.org/D153490
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
Index: llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
+++ llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
@@ -317,7 +317,7 @@
; CHECK-NEXT: $v10m2 = PseudoVLE16_V_M2 killed $x11, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v10 = VMV1R_V $v8
; CHECK-NEXT: $v11 = VMV1R_V $v9
- ; CHECK-NEXT: $v12m2 = PseudoVMV_V_V_M2 $v10m2, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2
$x0 = PseudoVSETVLI $x10, 201, implicit-def $vl, implicit-def $vtype
$v10m2 = PseudoVLE16_V_M2 killed $x11, $noreg, 4, implicit $vl, implicit $vtype
$v10 = COPY $v8
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -245,7 +245,7 @@
for (const MachineOperand &MO : MBBI->explicit_operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- if (!FoundDef && TRI->isSubRegisterEq(MO.getReg(), SrcReg)) {
+ if (!FoundDef && TRI->regsOverlap(MO.getReg(), SrcReg)) {
// We only permit the source of COPY has the same LMUL as the defined
// operand.
// There are cases we need to keep the whole register copy if the LMUL
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