[llvm] e345b9c - [NFC] Autogenerate CodeGen/PowerPC/pr40922.ll

Amaury Séchet via llvm-commits llvm-commits at lists.llvm.org
Sun Jun 25 14:06:56 PDT 2023


Author: Amaury Séchet
Date: 2023-06-25T21:05:06Z
New Revision: e345b9ca7ad2c6ff00479723a5974c969510f312

URL: https://github.com/llvm/llvm-project/commit/e345b9ca7ad2c6ff00479723a5974c969510f312
DIFF: https://github.com/llvm/llvm-project/commit/e345b9ca7ad2c6ff00479723a5974c969510f312.diff

LOG: [NFC] Autogenerate CodeGen/PowerPC/pr40922.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/pr40922.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/pr40922.ll b/llvm/test/CodeGen/PowerPC/pr40922.ll
index 983338a825900..9252e9a3e3aa4 100644
--- a/llvm/test/CodeGen/PowerPC/pr40922.ll
+++ b/llvm/test/CodeGen/PowerPC/pr40922.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
 
 ; Test case adapted from PR40922.
@@ -5,6 +6,39 @@
 @a.b = internal global i32 0, align 4
 
 define i32 @a() {
+; CHECK-LABEL: a:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    stwu 1, -32(1)
+; CHECK-NEXT:    stw 0, 36(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 4
+; CHECK-NEXT:    .cfi_offset r29, -12
+; CHECK-NEXT:    .cfi_offset r30, -8
+; CHECK-NEXT:    stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT:    bl d
+; CHECK-NEXT:    lis 29, a.b at ha
+; CHECK-NEXT:    lwz 4, a.b at l(29)
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    mr 30, 3
+; CHECK-NEXT:    addic 6, 4, 6
+; CHECK-NEXT:    addze 5, 5
+; CHECK-NEXT:    rlwinm 6, 6, 0, 28, 26
+; CHECK-NEXT:    andi. 5, 5, 1
+; CHECK-NEXT:    cmplw 1, 6, 4
+; CHECK-NEXT:    crorc 20, 1, 4
+; CHECK-NEXT:    bc 12, 20, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    bl e
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NEXT:    stw 30, a.b at l(29)
+; CHECK-NEXT:    lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 0, 36(1)
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
 entry:
   %call = tail call i32 @d()
   %0 = load i32, ptr @a.b, align 4
@@ -23,14 +57,6 @@ if.end:                                           ; preds = %if.then, %entry
   ret i32 undef
 }
 
-; CHECK-LABEL: @a
-; CHECK: li 5, 0
-; CHECK: mr 30, 3
-; CHECK: addic 6, 4, 6
-; CHECK: addze 5, 5
-; CHECK: rlwinm 6, 6, 0, 28, 26
-; CHECK: andi. 5, 5, 1
-
 declare i32 @d(...)
 
 declare i32 @e(...)


        


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