[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P

[Funan Zeng via Phabricator via llvm-commits]

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Rebase to main


Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153721

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
  llvm/test/MC/RISCV/corev/XCVsimd.s

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