[PATCH] D153234: [RISCV] Add codegen for Zfbfmin instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1846
     IsLegalVT = Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin();
+  else if (VT == MVT::bf16)
+    IsLegalVT = Subtarget.hasStdExtZfbfmin();
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Is this change tested?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:457
+// Moves (no conversion)
+def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
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These patterns duplicate patterns from HasStdExtZfhOrZfhmin, can we share them by using a new predicate?


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:245
 
+def BFPR16 : RegisterClass<"RISCV", [bf16], 16, (add
+    (sequence "F%u_H", 15, 10), // fa5-fa0
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Can we just add `bf16` to the type list for FPR16? If the only reason to have a separate register class is for tablegen type inference, I don't thinks that a good reason.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153234/new/

https://reviews.llvm.org/D153234