[PATCH] D153666: [RISCV] Add GPR bypasses for most scalar integer instructions to the SiFive7 scheduler model.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc accepted this revision.
wangpc added a comment.
This revision is now accepted and ready to land.

LGTM.
I don't know the details of macroarchitecture, but the change seems reasonable to me.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153666/new/

https://reviews.llvm.org/D153666