[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/docs/ReleaseNotes.rst:209
   disassembler/assembler.
+* Added support for the vendor-defined Xsfcie (SiFive SCIE) extension
+  disassembler/assembler.
----------------
SCIE->CIE since the S already stands for SiFive.


================
Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:562
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
+                          "SCIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
----------------
SCIE -> SiFive CIE


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370