[PATCH] D153506: [RISCV] Add a policy operand to VPseudoBinaryNoMaskTURoundingMode [NFC]
Yueh-Ting (eop) Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 23 07:39:34 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG703c1c7e784a: [RISCV] Add a policy operand to VPseudoBinaryNoMaskTURoundingMode [NFC] (authored by eopXD).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153506/new/
https://reviews.llvm.org/D153506
Files:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1196,13 +1196,14 @@
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
+ let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
}
@@ -4157,7 +4158,7 @@
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
(XLenVT timm:$round),
- GPR:$vl, sew)>;
+ GPR:$vl, sew, TU_MU)>;
// Same as above but source operands are swapped.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D153506.533963.patch
Type: text/x-patch
Size: 1078 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230623/94350a8d/attachment.bin>
More information about the llvm-commits
mailing list