[llvm] 703c1c7 - [RISCV] Add a policy operand to VPseudoBinaryNoMaskTURoundingMode [NFC]

[via llvm-commits]

Author: eopXD
Date: 2023-06-23T07:39:27-07:00
New Revision: 703c1c7e784a381fb92b5246b76794e48ed386fe

URL: https://github.com/llvm/llvm-project/commit/703c1c7e784a381fb92b5246b76794e48ed386fe
DIFF: https://github.com/llvm/llvm-project/commit/703c1c7e784a381fb92b5246b76794e48ed386fe.diff

LOG: [RISCV] Add a policy operand to VPseudoBinaryNoMaskTURoundingMode [NFC]

The template was created in D151396 but was not aware of the change in
D153067. This commit adds the operand and keep similar templates
aligned.

Reviewed By: reames, craig.topper

Differential Revision: https://reviews.llvm.org/D153506

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 3f570560b28a8..c36c97d1166ae 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1196,13 +1196,14 @@ class VPseudoBinaryNoMaskTURoundingMode<VReg RetClass,
                                         string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
-                    AVL:$vl, ixlenimm:$sew), []>,
+                    AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
   let HasVLOp = 1;
   let HasSEWOp = 1;
+  let HasVecPolicyOp = 1;
   let HasRoundModeOp = 1;
 }
 
@@ -4157,7 +4158,7 @@ class VPatBinaryNoMaskTURoundingMode<string intrinsic_name,
                    (op1_type op1_reg_class:$rs1),
                    (op2_type op2_kind:$rs2),
                    (XLenVT timm:$round),
-                   GPR:$vl, sew)>;
+                   GPR:$vl, sew, TU_MU)>;
 
 
 // Same as above but source operands are swapped.