[PATCH] D153034: [PowerPC][Future] Enable __builtin_mma_xxm[t|f]acc

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10716-10726
+    // Future cpu instructions dmxxinstdmr512 and dmxxextfdmr512 insert and
+    // extract quad vectors(v512i1) from the new wide accumulator(wacc)
+    // register class. The introduction of these new instructions renders the
+    // p10 instructions xxmtacc and xxmfacc obsolete since the new wacc
+    // register class is a better choice for handling quad vector operations.
+    // The intrinsics for xxmtacc and xxmfacc take one argument of
+    // type v512i1, a corresponding dmxx[inst|extf]dmr512 instruction
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I find it confusing to start talking about new instructions when the block starts with the p10 intrinsics. I would add this comment to after handling of non-future ISA code.  So after the if stmt and simplify it a bit as well.


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Comment at: llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll:152
+; CHECK-O0-NEXT:    lxv vs0, 32(r3)
+; CHECK-O0-NEXT:    # implicit-def: $vsrp17
+; CHECK-O0-NEXT:    xxlor v3, vs0, vs0
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I realized these -O0 run line was not added as part of this patch, but I am wondering why we need to be explicitly running `-O0` for these intrinsic tests.  Are they generated differently for `-O0` vs opt?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153034/new/

https://reviews.llvm.org/D153034