[PATCH] D143759: [AMDGPU] Implement whole wave register spill
Yashwant Singh via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 22 23:28:17 PDT 2023
yassingh updated this revision to Diff 533866.
yassingh added a comment.
- review comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143759/new/
https://reviews.llvm.org/D143759
Files:
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2222,9 +2222,9 @@
*MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
*MI->memoperands_begin(), RS);
- if (IsWWMRegSpill)
+ if (IsWWMRegSpill) {
TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy());
-
+ }
MI->eraseFromParent();
return true;
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D143759.533866.patch
Type: text/x-patch
Size: 624 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230623/69138961/attachment.bin>
More information about the llvm-commits
mailing list