[PATCH] D153519: [LegalizeTypes] Widen insert_subvector ops for fixed insert into scalable

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D153519#4441673 <https://reviews.llvm.org/D153519#4441673>, @luke wrote:

> In D153519#4441316 <https://reviews.llvm.org/D153519#4441316>, @craig.topper wrote:
>
>> Is it possible for the widened type to exceed the minimum vscale?
>
> Yes, but I think that would still fall under the "If this condition cannot be determined statically but is
> false at runtime, then the result vector is undefined." part of insert_subvector's definition. Since we currently already lower an insert_subvector of e.g. v8i32 into nxv4i32

What if vscale min is 3(not possible for RISC-V but this is generic code), and the types are nxv1i64 and v3i64. The operation is defined for those types, but when v3i64 gets widened to v4i64 it becomes undefined.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153519/new/

https://reviews.llvm.org/D153519