[PATCH] D153207: [AArch64] Add patterns for scalar FMUL, FMULX

Thu Jun 22 09:35:38 PDT 2023

dmgreen added a comment.

Thanks. That makes it clearer to read. Using the same patterns in SIMDFPIndexed is nice.

Can you make it so that t_vmulh_lane3_f16 is next to t_vmulh_lane_f16, and maybe rename t_vmulh_lane_f16 to t_vmulh_lane0_f16. So that they are still the same tests as before, but with the new additions inplace. The same for all the others.

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8541
+
+  def : Pat<(f32 (OpNode
+                   (f32 (vector_extract (v4f32 V128:$Rn), (i64 0))),
----------------
I think these should be HasNEON too.

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5231
+// Match scalar FMULX instead of indexed FMULX when extracting lane 0.
+let Predicates = [HasNEON, HasFullFP16] in {
+def : Pat<(f16 (int_aarch64_neon_fmulx
----------------
I don't think this needs NEON according to the reference I was looking at. Just FP.
The patterns for FMUL are very similar to the patterns for FMULX16. Could they share the same multiclass for the patterns?

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  https://reviews.llvm.org/D153207/new/

https://reviews.llvm.org/D153207