[PATCH] D153528: [PowerPC] Remove unused TableGen classes and multiclasses.
Ivan Kosarev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 22 04:04:34 PDT 2023
kosarev created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Herald added a project: All.
kosarev requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
And warn on them from now on.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D153528
Files:
llvm/lib/Target/PowerPC/CMakeLists.txt
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -75,8 +75,6 @@
class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
-class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
-class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
class XFormMemOp { bits<1> XFormMemOp = 1; }
@@ -120,11 +118,6 @@
bit Interpretation64Bit = 0;
}
-// Base class for all X-Form memory instructions
-class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin>
- :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
-
// 1.7.1 I-Form
class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
@@ -669,30 +662,6 @@
let Inst{31} = 0;
}
-class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
- let FRA = 0;
-}
-
-class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
- bits<5> FRT;
- bits<5> FRA;
- bits<5> FRB;
- bits<4> tttt;
-
- let Pattern = pattern;
-
- let Inst{6-10} = FRT;
- let Inst{11-15} = FRA;
- let Inst{16-20} = FRB;
- let Inst{21-24} = tttt;
- let Inst{25-30} = xo;
- let Inst{31} = 0;
-}
-
class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -270,14 +270,6 @@
!strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
[(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
-// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
-// inputs doesn't match the type of the output.
-class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
- ValueType InTy>
- : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
- !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
- [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
-
// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
// input types and an output type.
class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
Index: llvm/lib/Target/PowerPC/CMakeLists.txt
===================================================================
--- llvm/lib/Target/PowerPC/CMakeLists.txt
+++ llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -5,7 +5,7 @@
tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
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