[llvm] 5cd16e2 - [NFC SVE ACLE] Remove IR combines that no longer apply.

[Jolanta Jensen via llvm-commits]

Author: Jolanta Jensen
Date: 2023-06-22T10:26:20Z
New Revision: 5cd16e2cb7207a70a61d1221464b17dcaf3c7f29

URL: https://github.com/llvm/llvm-project/commit/5cd16e2cb7207a70a61d1221464b17dcaf3c7f29
DIFF: https://github.com/llvm/llvm-project/commit/5cd16e2cb7207a70a61d1221464b17dcaf3c7f29.diff

LOG: [NFC SVE ACLE] Remove IR combines that no longer apply.

Remove IR combines that no longer apply after the SVE merging
intrinsics taking an all active predicate, have been canonicalised
to their equivalent undef (_u) variants.

Differential Revision: https://reviews.llvm.org/D153415

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index ca3eb91d3c08d..630543aab2447 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1247,13 +1247,10 @@ instCombineSVEST1(InstCombiner &IC, IntrinsicInst &II, const DataLayout &DL) {
 
 static Instruction::BinaryOps intrinsicIDToBinOpCode(unsigned Intrinsic) {
   switch (Intrinsic) {
-  case Intrinsic::aarch64_sve_fmul:
   case Intrinsic::aarch64_sve_fmul_u:
     return Instruction::BinaryOps::FMul;
-  case Intrinsic::aarch64_sve_fadd:
   case Intrinsic::aarch64_sve_fadd_u:
     return Instruction::BinaryOps::FAdd;
-  case Intrinsic::aarch64_sve_fsub:
   case Intrinsic::aarch64_sve_fsub_u:
     return Instruction::BinaryOps::FSub;
   default:
@@ -1330,7 +1327,7 @@ instCombineSVEVectorFAdd(InstCombiner &IC, IntrinsicInst &II) {
                                             Intrinsic::aarch64_sve_fmla>(IC, II,
                                                                          true))
     return FMLA;
-  return instCombineSVEVectorBinOp(IC, II);
+  return std::nullopt;
 }
 
 static std::optional<Instruction *>
@@ -1372,7 +1369,7 @@ instCombineSVEVectorFSub(InstCombiner &IC, IntrinsicInst &II) {
                                             Intrinsic::aarch64_sve_fmls>(IC, II,
                                                                          true))
     return FMLS;
-  return instCombineSVEVectorBinOp(IC, II);
+  return std::nullopt;
 }
 
 static std::optional<Instruction *>