[PATCH] D153445: [SVE ACLE] Remove DAG combines that are no longer relevant.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll:269
   %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
   %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)
   %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
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mgabka wrote:
> @paulwalker-arm, I have a question here, what is the semantic of llvm.aarch64.sve.convert.from.svbool/ llvm.aarch64.sve.convert.to.svbool  ? 
`llvm.aarch64.sve.convert.from.svbool` returns a boolean vector that contains only those lanes that are relevant for the result type. For example, when the return type is `<vscale x 4 x i1>` it returns every 4th lane of the `<vscale x 16 x i1>` input.

`llvm.aarch64.sve.convert.to.svbool` returns a boolean vector of type `<vscale x 16 x i1>` whereby the input is evenly distributed, for example, when the input type is `<vscale x 2 x i1>` each input lane is distribute across every 8th lane of the result, with all other result lanes set to zero.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153445/new/

https://reviews.llvm.org/D153445