[PATCH] D153506: [RISCV] Add a policy operand to VPseudoBinaryNoMaskTURoundingMode [NFC]

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD created this revision.
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The template was created in D151396 <https://reviews.llvm.org/D151396> but was not aware of the change in
D153067 <https://reviews.llvm.org/D153067>. This commit adds the operand and keep similar templates
aligned.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153506

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1134,13 +1134,14 @@
                                         string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
-                    AVL:$vl, ixlenimm:$sew), []>,
+                    AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
   let HasVLOp = 1;
   let HasSEWOp = 1;
+  let HasVecPolicyOp = 1;
   let HasRoundModeOp = 1;
 }
 
@@ -4083,7 +4084,7 @@
                    (op1_type op1_reg_class:$rs1),
                    (op2_type op2_kind:$rs2),
                    (XLenVT timm:$round),
-                   GPR:$vl, sew)>;
+                   GPR:$vl, sew, TU_MU)>;
 
 
 // Same as above but source operands are swapped.


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