[llvm] 04a7c67 - [PhaseOrdering] Add test showing mis-compile caused by 17fdaccccf.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2023-06-21T21:15:14+01:00
New Revision: 04a7c672ab302d972ceabe43b1bbcdb2aa5ebe71

URL: https://github.com/llvm/llvm-project/commit/04a7c672ab302d972ceabe43b1bbcdb2aa5ebe71
DIFF: https://github.com/llvm/llvm-project/commit/04a7c672ab302d972ceabe43b1bbcdb2aa5ebe71.diff

LOG: [PhaseOrdering] Add test showing mis-compile caused by 17fdaccccf.

The test shows a mis-compile where @test gets incorrectly simplified to
unreachable. The test case is reduced from a ThinLTO build of Clang,
with only the relevant pass sequence included.

Added: 
    llvm/test/Transforms/PhaseOrdering/dse-ephemeral-value-captures.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/dse-ephemeral-value-captures.ll b/llvm/test/Transforms/PhaseOrdering/dse-ephemeral-value-captures.ll
new file mode 100644
index 0000000000000..aed2282265bca
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/dse-ephemeral-value-captures.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -passes='function(dse),cgscc(inline),function(sroa,gvn,sccp)' -S %s | FileCheck %s
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
+
+declare void @llvm.assume(i1 noundef)
+
+declare i1 @cond() #0
+
+define internal i1 @check_cond(ptr %a) #0 {
+  %l = load i32, ptr %a
+  %c = icmp eq i32 %l, 1
+  br i1 %c, label %then, label %else
+
+then:
+  %res = call i1 @cond()
+  ret i1 %res
+
+else:
+  ret i1 0
+}
+
+; FIXME: At the moment, the function is incorrectly simplified to unreachable.
+define i32 @test() {
+; CHECK-LABEL: define i32 @test() {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    unreachable
+;
+entry:
+  %a = alloca i32, align 4
+  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %a)
+  store i32 1, ptr %a, align 4
+  %res = call i1 @check_cond(ptr %a)
+  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %a)
+  call void @llvm.assume(i1 %res)
+  ret i32 0
+}
+
+attributes #0 = { nounwind readonly willreturn }