[llvm] 80e2c26 - RegisterCoalescer: Fix name of pass
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 21 07:31:21 PDT 2023
Author: Matt Arsenault
Date: 2023-06-21T10:30:43-04:00
New Revision: 80e2c26dfdd2e5ab1bbbf747ebff8c316399653c
URL: https://github.com/llvm/llvm-project/commit/80e2c26dfdd2e5ab1bbbf747ebff8c316399653c
DIFF: https://github.com/llvm/llvm-project/commit/80e2c26dfdd2e5ab1bbbf747ebff8c316399653c.diff
LOG: RegisterCoalescer: Fix name of pass
I finally snapped and fixed this inconsistency.
Added:
Modified:
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/test/CodeGen/AArch64/O3-pipeline.ll
llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
llvm/test/CodeGen/AArch64/regcoal-physreg.mir
llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
llvm/test/CodeGen/ARM/O3-pipeline.ll
llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
llvm/test/CodeGen/LoongArch/opt-pipeline.ll
llvm/test/CodeGen/M68k/pipeline.ll
llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
llvm/test/CodeGen/PowerPC/O3-pipeline.ll
llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll
llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll
llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
llvm/test/CodeGen/SystemZ/subregliveness-06.mir
llvm/test/CodeGen/SystemZ/subregliveness-07.mir
llvm/test/CodeGen/WebAssembly/regcoalesce-disable.ll
llvm/test/CodeGen/X86/adx-commute.mir
llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir
llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
llvm/test/CodeGen/X86/late-remat-update-2.mir
llvm/test/CodeGen/X86/late-remat-update.mir
llvm/test/CodeGen/X86/opt-pipeline.ll
llvm/test/CodeGen/X86/pre-coalesce.mir
llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir
llvm/test/Other/machine-size-remarks.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 4fc1d3ebc8d93..d1793015ae44a 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -398,14 +398,14 @@ char RegisterCoalescer::ID = 0;
char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
-INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
- "Simple Register Coalescing", false, false)
+INITIALIZE_PASS_BEGIN(RegisterCoalescer, "register-coalescer",
+ "Register Coalescer", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
- "Simple Register Coalescing", false, false)
+INITIALIZE_PASS_END(RegisterCoalescer, "register-coalescer",
+ "Register Coalescer", false, false)
[[nodiscard]] static bool isMoveInstr(const TargetRegisterInfo &tri,
const MachineInstr *MI, Register &Src,
@@ -4093,7 +4093,7 @@ void RegisterCoalescer::releaseMemory() {
}
bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
- LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
+ LLVM_DEBUG(dbgs() << "********** REGISTER COALESCER **********\n"
<< "********** Function: " << fn.getName() << '\n');
// Variables changed between a setjmp and a longjump can have undefined value
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index f6f98f9250bdb..92004996297da 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -160,7 +160,7 @@
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
index 6e444373047e4..3ff117f58aa77 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
@@ -4,7 +4,7 @@
#
# This test is for the problem from https://bugs.llvm.org/show_bug.cgi?id=38714.
#
-# Specifically, Simple Register Coalescing creates following conversion :
+# Specifically, Register Coalescer creates following conversion :
#
# undef %0.sub_32:gpr64 = ORRWrs $wzr, %3:gpr32common, 0, debug-location !24;
#
diff --git a/llvm/test/CodeGen/AArch64/regcoal-physreg.mir b/llvm/test/CodeGen/AArch64/regcoal-physreg.mir
index 270abeec822c0..d5e4742c3ffaf 100644
--- a/llvm/test/CodeGen/AArch64/regcoal-physreg.mir
+++ b/llvm/test/CodeGen/AArch64/regcoal-physreg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-apple-ios -run-pass=register-coalescer -verify-machineinstrs %s -o - | FileCheck %s
--- |
declare void @f2()
diff --git a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
index 85f6cbafd6037..f7b90868b2826 100644
--- a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
+++ b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
-# RUN: -run-pass simple-register-coalescing | FileCheck %s
+# RUN: -run-pass register-coalescer | FileCheck %s
# In this test case, the 32-bit copy implements a 32 to 64 bit zero extension
# and relies on the upper 32 bits being zeroed.
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir b/llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
index a480202e166f4..263d68294cd05 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-coalescing -verify-machineinstrs -start-before=simple-register-coalescing -stop-after=machine-scheduler -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-coalescing -verify-machineinstrs -start-before=register-coalescer -stop-after=machine-scheduler -o - %s | FileCheck %s
# Tests that break due to the handling of partially undef registers
# when whole register identity copies are erased.
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir b/llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
index fba3231ecfdff..45ccb4b8866e8 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-coalescing -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s
# Check that there's no "Live segment doesn't end at a valid
# instruction" failure after coalescing %0 into %2, which is
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir b/llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
index e454077655b15..1f235ebccfa33 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-coalescing -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s
# %2 has an undef read in %bb.3, and this IR wouldn't be valid if it
# was a real read. After merging %2 into %0, we need to replace the
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
index 78e5de1b18ddb..020e2de6d2b7f 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck %s
# Test used to crash with message:
# JoinVals::computeAssignment(unsigned int, (anonymous namespace)::JoinVals &): Assertion `Assignments[ValNo] != -1 && "Bad recursion?"' failed.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir b/llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
index 872959638cb6e..26723e1959571 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=register-coalescer -o - %s | FileCheck -check-prefix=GCN %s
# GCN: {{^body}}
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
index 280c82b3352c8..0d9987e45bdf8 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn--amdpal -run-pass=register-coalescer -o - %s | FileCheck %s
# Check that this doesn't crash. Check for some legitimate output.
# CHECK: S_CBRANCH_SCC1
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir b/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
index 0bfeffddc2f19..fe8fd03bf2a06 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx900 -o - -verify-coalescing -run-pass=simple-register-coalescing %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -o - -verify-coalescing -run-pass=register-coalescer %s | FileCheck -check-prefix=GCN %s
---
# Do not rematerialize V_MOV_B32 at COPY because source register %1 is killed.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir b/llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
index c77ce31b12607..64634af0a1e97 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
#
# The failure occurs when the coalescer tries to removePartialRedundency() on the
# "%2:vreg_64 = COPY %3" in bb.1. The coalescer tries to prune and extend each
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
index a077e67877bda..c656de046fd79 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=register-coalescer -o - %s | FileCheck -check-prefix=GCN %s
# With one version of the D48102 fix, this test failed with
# Assertion failed: (ValNo && "CopyMI input register not live"), function reMaterializeTrivialDef, file ../lib/CodeGen/RegisterCoalescer.cpp, line 1107.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
index 0fc299dae85d2..ac4f83b0a01ff 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=register-coalescer -o - %s | FileCheck -check-prefix=GCN %s
# With one version of the D48102 fix, this test failed with
# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2875.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
index c7c78bcbb0b67..899f2c1892ffa 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck -check-prefix=GCN %s
# Test used to crash with message:
# JoinVals::ConflictResolution (anonymous namespace)::JoinVals::analyzeValue(unsigned int, (anonymous namespace)::JoinVals &): Assertion `DefMI != nullptr' failed
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
index 34f83b0ae2ecb..317fbea3b7d46 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
# Check that %11 and %20 have been coalesced.
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG:[0-9]+]]
# CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG]]
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
index ad3143d6a8056..3ab3e4f35f2b0 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
#
# See bug http://llvm.org/PR33152 for details of the bug this test is checking
# for.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir b/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
index 65ca9cb06cfc8..9d9fb5685fa48 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=register-coalescer -o - %s | FileCheck -check-prefix=GCN %s
# With one version of the D48102 fix, this test failed with
# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2870.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
index 9f742041133e1..19924024a00dd 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
#
# This is another example of a test giving "Couldn't join subrange!"
#
diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
index 71e5ec7d52ed3..e066a48d9a3c2 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=register-coalescer,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
# This test is for a bug where the following happens:
#
diff --git a/llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir b/llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
index 01b8401fa25d2..eb0399cc81b2a 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
# Register coalescer is going to eliminate %2:sgpr_32 = COPY %1.sub0 from bb.1
# by joining %2 and %1.sub0 into %0.sub0 register. Check that when this happen
diff --git a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
index 893355b552fab..4d06f4a19597f 100644
--- a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
+++ b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s
#
---
name: _amdgpu_ps_main
diff --git a/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir b/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
index bef24bcfa2945..8dd5e239d94a2 100644
--- a/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
+++ b/llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# This is used to fail verififcation if MachineDCE tracks LIS.
diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
index c1896352ad87c..c34787307537b 100644
--- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
# Check that coalescer does not create wider register tuple than in source
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index 097f28e3fd8c4..bb482dbd93a87 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -340,7 +340,7 @@
; GCN-O1-NEXT: Slot index numbering
; GCN-O1-NEXT: Live Interval Analysis
; GCN-O1-NEXT: Machine Natural Loop Construction
-; GCN-O1-NEXT: Simple Register Coalescing
+; GCN-O1-NEXT: Register Coalescer
; GCN-O1-NEXT: Rename Disconnected Subregister Components
; GCN-O1-NEXT: Machine Instruction Scheduler
; GCN-O1-NEXT: MachinePostDominator Tree Construction
@@ -638,7 +638,7 @@
; GCN-O1-OPTS-NEXT: Slot index numbering
; GCN-O1-OPTS-NEXT: Live Interval Analysis
; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction
-; GCN-O1-OPTS-NEXT: Simple Register Coalescing
+; GCN-O1-OPTS-NEXT: Register Coalescer
; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
@@ -946,7 +946,7 @@
; GCN-O2-NEXT: Slot index numbering
; GCN-O2-NEXT: Live Interval Analysis
; GCN-O2-NEXT: Machine Natural Loop Construction
-; GCN-O2-NEXT: Simple Register Coalescing
+; GCN-O2-NEXT: Register Coalescer
; GCN-O2-NEXT: Rename Disconnected Subregister Components
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
; GCN-O2-NEXT: Machine Instruction Scheduler
@@ -1267,7 +1267,7 @@
; GCN-O3-NEXT: Slot index numbering
; GCN-O3-NEXT: Live Interval Analysis
; GCN-O3-NEXT: Machine Natural Loop Construction
-; GCN-O3-NEXT: Simple Register Coalescing
+; GCN-O3-NEXT: Register Coalescer
; GCN-O3-NEXT: Rename Disconnected Subregister Components
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
; GCN-O3-NEXT: Machine Instruction Scheduler
diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
index 3ba8289ebdd84..9e0231853d69a 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s
# REQUIRES: asserts
#
# This test will provoke a Couldn't join subrange unreachable without the
diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
index 2e0a96027068e..c07e4455f4d92 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
@@ -1,7 +1,7 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s
#
# See bug http://llvm.org/PR33524 for details of the problem being checked here
-# This test will provoke a subrange join (see annotations below) during simple register coalescing
+# This test will provoke a subrange join (see annotations below) during register coalescing
# Without a fix for PR33524 this causes an unreachable in SubRange Join
#
# GCN-DAG: undef %[[REG0:[0-9]+]].sub0:sgpr_64 = COPY $sgpr5
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
index 1ac68c2778cc0..9fec776df13f8 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
---
name: couldnt_join_subrange_implicit_def_pred_block
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
index 885907e4bee1e..757633dfd4bb8 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
# Test that register coalescing does not allow a call to
# LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
index cfdffaf2700c8..1c4900ae85f58 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
# Bug 39602: Avoid "Couldn't join subrange" error when clearing valid
# lanes on an implicit_def that later cannot be erased.
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
index 5664c7005b5dd..e18989c13476b 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s
+# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=register-coalescer | FileCheck %s
---
# Checks for a bug where subregister liveranges were not properly pruned for
# an IMPLCITI_DEF that gets removed completely.
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir b/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
index 75eebcdd3ab40..7a026242dd883 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
#
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir b/llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
index 9e4b076699279..f431eb0564be4 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
#
# This test gave "Use not jointly dominated by defs" when
# removePartialRedundancy attempted to prune and then re-extend a subrange.
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
index abddba4dfa569..dd61fc8da9610 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s
---
# GCN-LABEL: name: mac_invalid_operands
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
index 9a78bdff7fef1..47114c92d7958 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s
--- |
define amdgpu_kernel void @test0() { ret void }
define amdgpu_kernel void @test1() { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
index 6da316db0f0e4..d9c3d164fcadc 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-dce-in-ra=0 -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy,1 -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-dce-in-ra=0 -stress-regalloc=1 -start-before=register-coalescer -stop-after=greedy,1 -o - %s | FileCheck %s
# https://bugs.llvm.org/show_bug.cgi?id=33620
---
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
index 72cd2eec323fb..3b641092fb990 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.
---
diff --git a/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir b/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
index 5b1f420cce411..99c955319c648 100644
--- a/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-coalescing -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s
# The copy from %0 to %1 introduces liveness for %3.sub2. After
# coalescing, the use of %1.sub2 needs to be marked undef. The
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
index caae2747264d3..25d8961b0144a 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s
# Check that we get two move-immediates into %1 and %2, instead of a copy from
# %1 to %2, because that would introduce a dependency and maybe a stall.
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index 5bf56bca02416..5e565970fc3a8 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -122,7 +122,7 @@
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
index bba2024067984..8e60bb5281564 100644
--- a/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
+++ b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
@@ -1,4 +1,4 @@
-# RUN: llc --run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc --run-pass=register-coalescer -o - %s | FileCheck %s
# pr45489
# Coalescing variables across a setjmp call can add a undefined
# variable value when longjmp if such variables are spilled and
diff --git a/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir b/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
index 6503e5117d467..bf08af763357b 100644
--- a/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
+++ b/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -start-before simple-register-coalescing -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -arm-enable-subreg-liveness -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -arm-enable-subreg-liveness -verify-machineinstrs | FileCheck %s
# Check that when we merge live-ranges that imply offseting
# the definition of a subregister by some other subreg index,
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
index c60a93f8e33e0..16a22633e1459 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=hexagon -run-pass simple-register-coalescing -verify-coalescing %s -o - | FileCheck %s
+# RUN: llc -march=hexagon -run-pass register-coalescer -verify-coalescing %s -o - | FileCheck %s
#
# Check that this doesn't crash.
# CHECK: ENDLOOP
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
index 8fcac5d54f8b2..fac59950b1bc3 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=hexagon -run-pass=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=hexagon -run-pass=register-coalescer -o - %s | FileCheck %s
# Make sure that the coalescer does not create a full definition with
# an undef flag on the destination. This used to happen when rematerializing
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
index f31c5e572c95d..8cb88ae5949ca 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass simple-register-coalescing %s -o - | FileCheck %s
+# RUN: llc -march=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass register-coalescer %s -o - | FileCheck %s
#
# If there is no consumer of the live intervals, the live intervals pass
# will be freed immediately after it runs, before the verifier. Add a
diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
index d57325e5b27db..f4a623d74436f 100644
--- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
+++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
@@ -1,8 +1,8 @@
-# Using a trick to run simple-register-coalescing twice, that way
+# Using a trick to run register-coalescer twice, that way
# liveintervals should be preserved while running the machine verifier.
#
-# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
-# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
+# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
+# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
---
name: test_pass
diff --git a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
index f3c160b789b47..8b1d635b605b3 100644
--- a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
+++ b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
@@ -113,7 +113,7 @@
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/M68k/pipeline.ll b/llvm/test/CodeGen/M68k/pipeline.ll
index e936abf7f568f..dfaa149b7a474 100644
--- a/llvm/test/CodeGen/M68k/pipeline.ll
+++ b/llvm/test/CodeGen/M68k/pipeline.ll
@@ -84,7 +84,7 @@
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
index f442566dd60ba..d57c3edd480e2 100644
--- a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
+++ b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -o - %s -run-pass=simple-register-coalescing | FileCheck %s
+# RUN: llc -march=mips64 -o - %s -run-pass=register-coalescer | FileCheck %s
---
name: f
diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
index cc5d4b1aa125c..0b6b5d752298d 100644
--- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -154,7 +154,7 @@
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: PowerPC VSX FMA Mutation
diff --git a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
index 2f32d53ace30e..15b7dc1a38fab 100644
--- a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -1,9 +1,9 @@
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; This file mainly tests that one of the ISEL instruction in the group uses the same register for operand RT, RA, RB
-; This redudant ISEL is introduced during simple register coalescing stage.
+; This redudant ISEL is introduced during register coalescing stage.
-; Simple register coalescing first create the foldable ISEL instruction as we have seen in expand-foldable-isel.ll:
+; Register coalescing first create the foldable ISEL instruction as we have seen in expand-foldable-isel.ll:
; %vreg85<def> = ISEL8 %vreg83, %vreg83, %vreg33:sub_eq
; Later the register coalescer figures out it could further coalesce %vreg85 with %vreg83:
diff --git a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
index 8f671bc9bfe01..4396b0a4ed3b7 100644
--- a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
@@ -2,12 +2,12 @@
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; This file mainly tests the case that the two input registers of the ISEL instruction are the same register.
-; The foldable ISEL in this test case is introduced at simple register coalescing stage.
+; The foldable ISEL in this test case is introduced at register coalescing stage.
; Before that stage we have:
; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>;
-; At simple register coalescing stage, the register coalescer figures out it could remove the copy
+; At register coalescing stage, the register coalescer figures out it could remove the copy
; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly
; erased: 336r %vreg5<def> = COPY %vreg2
; updated: 288B %vreg5<def> = COPY %X3;
diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll
index 668584a1aabc5..0653d4ef6fd0a 100644
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll
@@ -1,16 +1,16 @@
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small \
-; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: -stop-after=machine-cp -print-before=register-coalescer 2>&1 < \
; RUN: %s | FileCheck --check-prefix=SMALL %s
; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \
; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large \
-; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: -stop-after=machine-cp -print-before=register-coalescer 2>&1 < \
; RUN: %s | FileCheck --check-prefix=LARGE %s
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp \
-; RUN: -print-before=simple-register-coalescing 2>&1 < %s | FileCheck \
+; RUN: -print-before=register-coalescer 2>&1 < %s | FileCheck \
; RUN: --check-prefix=SMALL %s
@msg = common global ptr null, align 4
diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll
index c4f4812609555..a1d0dc57619a5 100644
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll
@@ -1,16 +1,16 @@
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small \
-; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: -stop-after=machine-cp -print-before=register-coalescer 2>&1 < \
; RUN: %s | FileCheck --check-prefix=SMALL %s
; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \
; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large \
-; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: -stop-after=machine-cp -print-before=register-coalescer 2>&1 < \
; RUN: %s | FileCheck --check-prefix=LARGE %s
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp \
-; RUN: -print-before=simple-register-coalescing 2>&1 < %s | FileCheck \
+; RUN: -print-before=register-coalescer 2>&1 < %s | FileCheck \
; RUN: --check-prefix=SMALL %s
@msg = common global ptr null, align 8
diff --git a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
index 67b64b447a5fa..3a312d2f4a8ba 100644
--- a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
+++ b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass simple-register-coalescing %s -o - | FileCheck %s
+# RUN: llc -run-pass register-coalescer %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
@@ -168,7 +168,7 @@ body: |
BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...
-#Copy of CRUNSET should be removed in simple register coalescing pass
+#Copy of CRUNSET should be removed in register coalescing pass
#CHECK-LABEL: copycrunset
#CHECK: bb.1.while.body.preheader:
#CHECK-NOT: %9:crbitrc = CRUNSET
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index aa92f2d8bc32c..4c6c28a3bb20b 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -119,7 +119,7 @@
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
index 1a71c8f5fb7d6..9a338a058ed1c 100644
--- a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
+++ b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
@@ -1,5 +1,5 @@
# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 \
-# RUN: -start-before=simple-register-coalescing -o - 2>&1 > /dev/null
+# RUN: -start-before=register-coalescer -o - 2>&1 > /dev/null
# Test that the SystemZ shouldCoalesce() implementation does not crash in
# case of an undef use in another MBB. This was discovered in testing with
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
index de7e4647551fc..f7b58f04fd7ba 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mcpu=z13 -O3 -misched=ilpmin -systemz-subreg-liveness -verify-machineinstrs -start-before simple-register-coalescing %s -mtriple s390x-ibm-linux -stop-after machine-scheduler -o - | FileCheck %s
+# RUN: llc -mcpu=z13 -O3 -misched=ilpmin -systemz-subreg-liveness -verify-machineinstrs -start-before register-coalescer %s -mtriple s390x-ibm-linux -stop-after machine-scheduler -o - | FileCheck %s
# Check that when the register coalescer rematerializes a register to set
# only a sub register, it sets the subranges of the unused lanes as being dead
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
index cb5f422a04891..f709b70ff1b79 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before simple-register-coalescing -stop-after greedy -o - %s | FileCheck %s
+# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before register-coalescer -stop-after greedy -o - %s | FileCheck %s
# Check that when we split the live-range with several active lanes
# as part of the live-range update, we correctly eliminate the VNI from
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
index 177afcd73e822..b1a0a309e1e20 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass simple-register-coalescing %s -systemz-subreg-liveness -O3 -mtriple s390x-ibm-linux -mcpu z13 -o - | FileCheck %s
+# RUN: llc -run-pass register-coalescer %s -systemz-subreg-liveness -O3 -mtriple s390x-ibm-linux -mcpu z13 -o - | FileCheck %s
#
# When the coalescing tries to coalesce `%20 = COPY %18`,
# %18 has been coalesced all the way up to %15 = ROSBG.
diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir
index d93232a695d21..1ca1114be6684 100644
--- a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir
+++ b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -misched=shuffle -verify-machineinstrs -start-before=simple-register-coalescing -systemz-subreg-liveness %s -o - | FileCheck %s
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -misched=shuffle -verify-machineinstrs -start-before=register-coalescer -systemz-subreg-liveness %s -o - | FileCheck %s
# -misched=shuffle is under !NDEBUG.
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir
index f3e190392e0be..d12524b800324 100644
--- a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir
+++ b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=s390x-ibm-linux -systemz-subreg-liveness -verify-machineinstrs -start-before=simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=s390x-ibm-linux -systemz-subreg-liveness -verify-machineinstrs -start-before=register-coalescer -o - %s | FileCheck %s
# Check for successful compilation.
# CHECK: lhi %r0, 0
diff --git a/llvm/test/CodeGen/WebAssembly/regcoalesce-disable.ll b/llvm/test/CodeGen/WebAssembly/regcoalesce-disable.ll
index 82d99d2b75b20..7a44418e23b9f 100644
--- a/llvm/test/CodeGen/WebAssembly/regcoalesce-disable.ll
+++ b/llvm/test/CodeGen/WebAssembly/regcoalesce-disable.ll
@@ -3,8 +3,8 @@
; Test if RegisterCoalesce pass is disabled in -O1.
-; O1-NOT: Simple Register Coalescing
-; O2: Simple Register Coalescing
+; O1-NOT: Register Coalescer
+; O2: Register Coalescer
target triple = "wasm32-unknown-unknown"
define void @test() {
diff --git a/llvm/test/CodeGen/X86/adx-commute.mir b/llvm/test/CodeGen/X86/adx-commute.mir
index 5683d0610de52..aa20084f7cd9e 100644
--- a/llvm/test/CodeGen/X86/adx-commute.mir
+++ b/llvm/test/CodeGen/X86/adx-commute.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - -mtriple=x86_64-- -run-pass=twoaddressinstruction,simple-register-coalescing %s | FileCheck %s
+# RUN: llc -o - -mtriple=x86_64-- -run-pass=twoaddressinstruction,register-coalescer %s | FileCheck %s
# Tests for commuting ADCX and ADOX to avoid copies. The ADOX tests were manually constructed by modifying ADCX tests to use OF instead of CF.
--- |
; ModuleID = 'test.ll'
diff --git a/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir b/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
index 8fa3d82a96694..ed89609b143a3 100644
--- a/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
+++ b/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple x86_64-pc-linux-gnu -run-pass simple-register-coalescing -verify-coalescing -o - %s | FileCheck %s
+# RUN: llc -O0 -mtriple x86_64-pc-linux-gnu -run-pass register-coalescer -verify-coalescing -o - %s | FileCheck %s
--- |
define i16 @main() {
diff --git a/llvm/test/CodeGen/X86/coalesce-dead-lanes.mir b/llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
index 6c9e9ad81f15c..f599ed00a3e5c 100644
--- a/llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
+++ b/llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass simple-register-coalescing -O0 -mtriple x86_64-pc-linux-gnu -o - %s | FileCheck %s
+# RUN: llc -run-pass register-coalescer -O0 -mtriple x86_64-pc-linux-gnu -o - %s | FileCheck %s
---
name: foo
diff --git a/llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir b/llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir
index 3a67cf67be8ea..57ab79c3f6d22 100644
--- a/llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir
+++ b/llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O1 -start-after simple-register-coalescing -o - %s -experimental-debug-variable-locations=false | FileCheck %s
+# RUN: llc -O1 -start-after register-coalescer -o - %s -experimental-debug-variable-locations=false | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
index 6bb05dea4b5e1..86319da8db018 100644
--- a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
+++ b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O1 -start-after simple-register-coalescing -o - %s -experimental-debug-variable-locations=true | FileCheck %s
+# RUN: llc -O1 -start-after register-coalescer -o - %s -experimental-debug-variable-locations=true | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/X86/late-remat-update-2.mir b/llvm/test/CodeGen/X86/late-remat-update-2.mir
index 5948e258867e3..3ffcb2fdf9e40 100644
--- a/llvm/test/CodeGen/X86/late-remat-update-2.mir
+++ b/llvm/test/CodeGen/X86/late-remat-update-2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-- -run-pass=simple-register-coalescing -run-pass=regallocbasic -run-pass=virtregrewriter -late-remat-update-threshold=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -run-pass=register-coalescer -run-pass=regallocbasic -run-pass=virtregrewriter -late-remat-update-threshold=0 %s -o - | FileCheck %s
#
# PR40061: %t2 = %t1 is rematerialized and %t1 is added into toBeUpdated set
# to postpone its live interval update. After the rematerialization, the live
diff --git a/llvm/test/CodeGen/X86/late-remat-update.mir b/llvm/test/CodeGen/X86/late-remat-update.mir
index da7b9e11820d1..84a78f84728ca 100644
--- a/llvm/test/CodeGen/X86/late-remat-update.mir
+++ b/llvm/test/CodeGen/X86/late-remat-update.mir
@@ -1,5 +1,5 @@
# REQUIRES: asserts
-# RUN: llc -mtriple=x86_64-- -run-pass=simple-register-coalescing -late-remat-update-threshold=1 -stats %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -run-pass=register-coalescer -late-remat-update-threshold=1 -stats %s -o /dev/null 2>&1 | FileCheck %s
# Check the test will rematerialize for three copies, but will call shrinkToUses
# only once to update live range because of late rematerialization update.
# CHECK: 3 regalloc - Number of instructions re-materialized
diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll
index 556a2be0b138a..fb8d2335b3410 100644
--- a/llvm/test/CodeGen/X86/opt-pipeline.ll
+++ b/llvm/test/CodeGen/X86/opt-pipeline.ll
@@ -138,7 +138,7 @@
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
-; CHECK-NEXT: Simple Register Coalescing
+; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/X86/pre-coalesce.mir b/llvm/test/CodeGen/X86/pre-coalesce.mir
index 925cc4ba221b2..107f8944a729b 100644
--- a/llvm/test/CodeGen/X86/pre-coalesce.mir
+++ b/llvm/test/CodeGen/X86/pre-coalesce.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass register-coalescer -o - %s | FileCheck %s
# Check there is no partial redundent copy left in the loop after register coalescing.
--- |
; ModuleID = '<stdin>'
diff --git a/llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir b/llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir
index d99a70820681f..11387521b84df 100644
--- a/llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir
+++ b/llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir
@@ -1,4 +1,4 @@
-# RUN: llc < %s -x=mir -mtriple=x86_64-- -run-pass=simple-register-coalescing | FileCheck %s
+# RUN: llc < %s -x=mir -mtriple=x86_64-- -run-pass=register-coalescer | FileCheck %s
---
name: f
body: |
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
index 5fa89bfbd8467..aae2f3870138c 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
@@ -1,5 +1,5 @@
# REQUIRES: asserts
-# RUN: llc -x mir -run-pass=simple-register-coalescing,greedy -verify-machineinstrs < %s 2>&1 | FileCheck %s
+# RUN: llc -x mir -run-pass=register-coalescer,greedy -verify-machineinstrs < %s 2>&1 | FileCheck %s
# CHECK-NOT: Bad Parent VNI
--- |
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
index 9fef2904eb892..87f5f0f96c505 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -x mir -run-pass=simple-register-coalescing,greedy -verify-machineinstrs < %s | FileCheck %s
+# RUN: llc -x mir -run-pass=register-coalescer,greedy -verify-machineinstrs < %s | FileCheck %s
## Check that Inline Spiller cannot insert spill after last insertion point.
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
index 115d4110a4715..858ff3f1888b9 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
@@ -1,4 +1,4 @@
-# RUN: llc -x mir -o - %s -run-pass=twoaddressinstruction,simple-register-coalescing,greedy -verify-regalloc 2>&1 | FileCheck %s
+# RUN: llc -x mir -o - %s -run-pass=twoaddressinstruction,register-coalescer,greedy -verify-regalloc 2>&1 | FileCheck %s
# The test checks no verification errors happen in the case of
# statepoint invoke instruction with tied-defs.
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
index a2f991074671e..51d3f7e1a6a4e 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
@@ -1,7 +1,7 @@
# RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
# RUN: -experimental-debug-variable-locations \
# RUN: -start-before=phi-node-elimination \
-# RUN: -stop-after=simple-register-coalescing \
+# RUN: -stop-after=register-coalescer \
# RUN: | FileCheck %s --check-prefix=DOESCOALESCE
# RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
# RUN: -experimental-debug-variable-locations \
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
index b4172bd5f008a..bc1c7ebac6cef 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
@@ -1,10 +1,10 @@
# RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
# RUN: -experimental-debug-variable-locations \
-# RUN: -run-pass=phi-node-elimination,simple-register-coalescing \
+# RUN: -run-pass=phi-node-elimination,register-coalescer \
# RUN: | FileCheck %s --check-prefix=DOESCOALESCE
# RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
# RUN: -experimental-debug-variable-locations \
-# RUN: -run-pass=phi-node-elimination,simple-register-coalescing,livedebugvars,greedy,virtregrewriter \
+# RUN: -run-pass=phi-node-elimination,register-coalescer,livedebugvars,greedy,virtregrewriter \
# RUN: | FileCheck %s --check-prefix=CHECK
#
# Test that a PHI with a debug instruction number attached survives register
diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
index 581375b6b2875..30c3bd27b0a2a 100644
--- a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
+++ b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -start-before=simple-register-coalescing -stop-after=simple-register-coalescing | FileCheck %s
+# RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -start-before=register-coalescer -stop-after=register-coalescer | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir
index c1d361a209a7b..e2b8fa272d10e 100644
--- a/llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir
+++ b/llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-unknown-unknown %s -o - -run-pass=simple-register-coalescing | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-unknown %s -o - -run-pass=register-coalescer | FileCheck %s
# PR40010: DBG_VALUEs do not contribute to the liveness of virtual registers,
# and the register coalescer would merge new live values on top of DBG_VALUEs,
# leading to them presenting new (wrong) values to the debugger. Test that
diff --git a/llvm/test/Other/machine-size-remarks.ll b/llvm/test/Other/machine-size-remarks.ll
index 2a32e63a85ca2..90d081ea8a60c 100644
--- a/llvm/test/Other/machine-size-remarks.ll
+++ b/llvm/test/Other/machine-size-remarks.ll
@@ -15,7 +15,7 @@
; CHECK: remark: <unknown>:0:0: X86 DAG->DAG Instruction Selection: Function:
; CHECK-SAME: main: MI Instruction count changed from 0
; CHECK-SAME: to [[INIT:[1-9][0-9]*]]; Delta: [[INIT]]
-; CHECK-NEXT: remark: <unknown>:0:0: Simple Register Coalescing: Function: main:
+; CHECK-NEXT: remark: <unknown>:0:0: Register Coalescer: Function: main:
; CHECK-SAME: MI Instruction count changed from [[INIT]] to
; CHECK-SAME: [[FINAL:[1-9][0-9]*]];
; CHECK-SAME: Delta: [[DELTA:-?[1-9][0-9]*]]
@@ -39,7 +39,7 @@
; CHECK-NEXT: Name: FunctionMISizeChange
; CHECK-NEXT: Function: main
; CHECK-NEXT: Args:
-; CHECK-NEXT: - Pass: Simple Register Coalescing
+; CHECK-NEXT: - Pass: Register Coalescer
; CHECK-NEXT: - String: ': Function: '
; CHECK-NEXT: - Function: main
; CHECK-NEXT: - String: ': '
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