[PATCH] D143759: [AMDGPU] Implement whole wave register spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1471
 
+  const TargetRegisterClass &RC = ST.isWave32()
+                                      ? AMDGPU::SReg_32_XM0_XEXECRegClass
----------------
ST.getWaveMaskRegClass


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1473
+                                      ? AMDGPU::SReg_32_XM0_XEXECRegClass
+                                      : AMDGPU::SGPR_64RegClass;
+
----------------
This misses VCC as a possibility, which is fixed by using getWaveMaskRegClass


================
Comment at: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp:338
+    const TargetRegisterClass *RC =
+        ST.isWave32() ? &AMDGPU::SGPR_32RegClass : &AMDGPU::SGPR_64RegClass;
+    // Shift back the reserved SGPR for EXEC copy into the lowest range.
----------------
Same, use getWaveMaskRegClass


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143759/new/

https://reviews.llvm.org/D143759