[llvm] c68c6c5 - [AMDGPU] Minor refactoring in SILoadStoreOptimizer::offsetsCanBeCombined

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-06-21T12:05:47+01:00
New Revision: c68c6c56fc53f560a0c1d8f5ed80c724b70c30b5

URL: https://github.com/llvm/llvm-project/commit/c68c6c56fc53f560a0c1d8f5ed80c724b70c30b5
DIFF: https://github.com/llvm/llvm-project/commit/c68c6c56fc53f560a0c1d8f5ed80c724b70c30b5.diff

LOG: [AMDGPU] Minor refactoring in SILoadStoreOptimizer::offsetsCanBeCombined

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index a0f782c6b9f99..c252d30e250e2 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -959,9 +959,12 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
 
   // Handle all non-DS instructions.
   if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {
-    return (EltOffset0 + CI.Width == EltOffset1 ||
-            EltOffset1 + Paired.Width == EltOffset0) &&
-           CI.CPol == Paired.CPol;
+    if (EltOffset0 + CI.Width != EltOffset1 &&
+            EltOffset1 + Paired.Width != EltOffset0)
+      return false;
+    if (CI.CPol != Paired.CPol)
+      return false;
+    return true;
   }
 
   // If the offset in elements doesn't fit in 8-bits, we might be able to use