[PATCH] D153346: [BOLT][RISCV] Add tests for simple CFG transformations

[Job Noorman via Phabricator via llvm-commits]

jobnoorman added inline comments.


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Comment at: bolt/test/RISCV/internal-func-reloc.s:12
+  /// These options are only used to make the assembler output easier to predict
+  .option norelax
+  .option norvc
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rafauler wrote:
> This is something we might want to ask of binaries that intend to be BOLTed, as BOLT is going to do a lot of things that RISCV is attempting to do with linkers and linker relaxation. This is specially true if BOLT later reorders functions in a way that now requires thunks/stubs insertion to extend the range of branches that got prematurely relaxed by the linker.
My hope is that this won't be necessary, as it goes against the idea of BOLT working on production binaries where linker relaxation will most certainly be enabled for RISC-V.

I have a WIP patch that tries to deal with this (in a nutshell: "unrelax" instructions in BOLT and let JITLink relax them again later, if possible) that I hope to be able to post later this week.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153346/new/

https://reviews.llvm.org/D153346