[PATCH] D146554: [BOLT][RISCV] Implement R_RISCV_ADD32/SUB32

[Rafael Auler via Phabricator via llvm-commits]

rafauler added inline comments.


================
Comment at: bolt/lib/Rewrite/RewriteInstance.cpp:2906
+      (opts::ForceToDataRelocations && checkMaxDataRelocations()) ||
+      // RISC-V has ADD/SUB data-to-data relocations
+      BC->isRISCV())
----------------
Aren't these data-to-code relocs? (BOLT doesn't need to update data-to-data relocs).


================
Comment at: bolt/test/RISCV/reloc-jt.s:13-14
+.LBB0_0:
+  auipc a1, %pcrel_hi(.LJTI0_0)
+  addi a1, a1, %pcrel_lo(.LBB0_0)
+  lw a0, (a1)
----------------
I'm not sure I get that. Aren't the two relocs supposed to point to the same symbol (.LJTI0_0)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146554/new/

https://reviews.llvm.org/D146554