[PATCH] D153129: [AArch64][RCPC3] Instruction selection for LDAP1/STL1 instructions

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'd like to see test coverage for load/store of:

- a plain non-vector double value
- 64-bit vectors
- insert/extract from SVE vectors
- inserting into lane zero of a <2 x i64> vector

(I'm not expecting any particular result for the above, but I'd like to see what happens beyond the exact patterns you've implemented.)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153129/new/

https://reviews.llvm.org/D153129