[llvm] ff23856 - [DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-06-20T15:31:22+01:00
New Revision: ff23856c1c0cc4a8737e7338b084297e6877e910

URL: https://github.com/llvm/llvm-project/commit/ff23856c1c0cc4a8737e7338b084297e6877e910
DIFF: https://github.com/llvm/llvm-project/commit/ff23856c1c0cc4a8737e7338b084297e6877e910.diff

LOG: [DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive

This is a generic DAG combine version of D151055 which recognizes when a signed ABDS can be safely replaced with a unsigned ABDU instruction if it is legal.

Alive2: https://alive2.llvm.org/ce/z/pb5BjG

Differential Revision: https://reviews.llvm.org/D153328

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 56dc284adf709..40aedeca2b061 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5207,6 +5207,11 @@ SDValue DAGCombiner::visitABD(SDNode *N) {
   if (N0.isUndef() || N1.isUndef())
     return DAG.getConstant(0, DL, VT);
 
+  // fold (abds x, y) -> (abdu x, y) iff both args are known positive
+  if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) &&
+      DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
+    return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
+
   return SDValue();
 }
 

diff  --git a/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll b/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
index 870403cb658f9..787b81f7f2098 100644
--- a/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
@@ -20,17 +20,11 @@ define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) {
 ; CHECK-NEXT:    vperm 1, 4, 3, 1
 ; CHECK-NEXT:    vperm 2, 4, 2, 7
 ; CHECK-NEXT:    vperm 3, 4, 3, 7
-; CHECK-NEXT:    xvnegsp 36, 38
-; CHECK-NEXT:    xvnegsp 35, 35
-; CHECK-NEXT:    xvnegsp 34, 34
-; CHECK-NEXT:    vabsduw 2, 2, 3
-; CHECK-NEXT:    xvnegsp 35, 33
-; CHECK-NEXT:    vabsduw 3, 4, 3
-; CHECK-NEXT:    xvnegsp 36, 37
-; CHECK-NEXT:    xvnegsp 37, 32
-; CHECK-NEXT:    vpkuwum 2, 2, 2
-; CHECK-NEXT:    vabsduw 4, 5, 4
+; CHECK-NEXT:    vabsduw 4, 5, 0
+; CHECK-NEXT:    vabsduw 2, 3, 2
+; CHECK-NEXT:    vabsduw 3, 1, 6
 ; CHECK-NEXT:    vpkuwum 3, 4, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
 ; CHECK-NEXT:    vpkuhum 2, 2, 3
 ; CHECK-NEXT:    blr
 entry: