[PATCH] D153328: [DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: lkail, dmgreen, shchenz, qiucf, nemanjai.
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This is a generic DAG combine version of D151055 <https://reviews.llvm.org/D151055> which recognizes when a signed ABDS can be safely replaced with a unsigned ABDU instruction if it has better legality.

Alive2: https://alive2.llvm.org/ce/z/pb5BjG


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153328

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll


Index: llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
+++ llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
@@ -20,17 +20,11 @@
 ; CHECK-NEXT:    vperm 1, 4, 3, 1
 ; CHECK-NEXT:    vperm 2, 4, 2, 7
 ; CHECK-NEXT:    vperm 3, 4, 3, 7
-; CHECK-NEXT:    xvnegsp 36, 38
-; CHECK-NEXT:    xvnegsp 35, 35
-; CHECK-NEXT:    xvnegsp 34, 34
-; CHECK-NEXT:    vabsduw 2, 2, 3
-; CHECK-NEXT:    xvnegsp 35, 33
-; CHECK-NEXT:    vabsduw 3, 4, 3
-; CHECK-NEXT:    xvnegsp 36, 37
-; CHECK-NEXT:    xvnegsp 37, 32
-; CHECK-NEXT:    vpkuwum 2, 2, 2
-; CHECK-NEXT:    vabsduw 4, 5, 4
+; CHECK-NEXT:    vabsduw 4, 5, 0
+; CHECK-NEXT:    vabsduw 2, 3, 2
+; CHECK-NEXT:    vabsduw 3, 1, 6
 ; CHECK-NEXT:    vpkuwum 3, 4, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
 ; CHECK-NEXT:    vpkuhum 2, 2, 3
 ; CHECK-NEXT:    blr
 entry:
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5207,6 +5207,11 @@
   if (N0.isUndef() || N1.isUndef())
     return DAG.getConstant(0, DL, VT);
 
+  // fold (abds x, y) -> (abdu x, y) iff both args are known positive
+  if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) &&
+      DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
+    return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
+
   return SDValue();
 }
 


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