[PATCH] D143759: [AMDGPU] Implement whole wave register spill
Yashwant Singh via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 20 03:23:13 PDT 2023
yassingh added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:651
+ assert(Reg.isVirtual());
+ if (VRegFlags.inBounds(Reg))
+ VRegFlags[Reg] |= (uint8_t)1 << Flag;
----------------
arsenm wrote:
> cdevadas wrote:
> > arsenm wrote:
> > > Why are the inbounds checks needed? The analagous MRI functions do not tolerate invalid register values
> > VRegFlags will be grown each time (if the size exceeds the initial size set) when a new virtual register is created/cloned. The MRI's 'VRegToType' has a similar bound check.
> VRegToType isn't really analagous. Untyped and typed registers can coexist, I'd expect it to be unnecessary here
Getting rid of inbounds check causes multiple test failures. (In spill192.mir, spill224.mir, spill288.mir, spill320.mir, etc).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143759/new/
https://reviews.llvm.org/D143759
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