[PATCH] D152827: [AArch64] Correctly determine if {ADD,SUB}{W,X}rs instructions are cheap

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 20 02:20:39 PDT 2023

dmgreen added a comment.

Adding handling for ADDWrs with LSLFast sounds good to me. I'm not so sure about this CustomCheapAsMoveHandling though. Ignoring the fact that isCheapAsMove is a bit of a strange concept nowadays, it seems to be missing some of the instructions usually marked as isAsCheapAsAMove (things like COPY and IMPLICIT_DEF, as well as target nodes like FMOV's and MOVI's). I would also like it if either all cpus used hasCustomCheapAsMoveHandling (especially for the testing) or if they were at least closer in terms of functionality.

Do we think that isAsCheapAsAMove should be all instructions that are really as cheap as a mov? (As in, zero latency move instructions, handled in rename). Or should it be all instructions that are single cycle, like ADDs and ORRs, etc?

Do you have any performance results? And can you add a test.



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