[PATCH] D153316: [AArch64][SelectionDAG] fix infinite loop caused by legalizing & combining CONCAT_VECTORS

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Please regenerate the diff with context



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23176
+    // AArch64TargetLowering::LowerCONCAT_VECTORS() and only when LegalDAG is
+    // true. The corresponding combining happens here.
+    //
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We don't usually refer to issue# in code - we add that to the tests instead. The description here should be more generic


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23180
+    // make sure targets which does not support SVE are not affected by this
+    // change.
+    if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
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The comment doesn't appear to match the code - the code just prevents folding scalable vectors after LegalDAG.


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Comment at: llvm/test/CodeGen/AArch64/aarch64-sve-concat_vectors.ll:2
+; RUN: llc -O3 -mcpu=neoverse-n2 < %s | FileCheck %s
+; CHECK: @allocno_reload_assign
+
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Better to use the update_llc_test_checks script


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Comment at: llvm/test/CodeGen/AArch64/aarch64-sve-concat_vectors.ll:18
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn writeonly }
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remove the unnecessary metadata etc.


Repository:
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  https://reviews.llvm.org/D153316/new/

https://reviews.llvm.org/D153316